High-Efficiency high-gain 2.4 GHz class-b power amplifiers in 0.13 µm cmos for wireless communications

lifiers. 
implementation due to technology limitations Section 3 introduces the architectures of the 
such as low breakdown voltage and poor proposed class-B PAs including detailed 
 descriptions of the circuit topologies. The 
_______ simulation results are presented in section 4 and 
*
 Corresponding author. E-mail.: tanhvu@vnu.edu.vn conclusions are given in the last section. 
 https://doi.org/10.25073/2588-1086/vnucsce.151 
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2 T.A. Vu et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 33, No. 1 (2017) 1-7 
2. Poweramplifierbasics 
2.1. PA block diagram 
 The general design concept of a PA is given 
in Fig. 1. The two port network is applied in the 
design consisting of two matching networks 
that are used on both sides of the power 
transistor. Maximum gain will be realized when 
the matching networks provide a conjugate 
match between the source/load impedance and 
the transistor impedance [6]. Specifically, the Figure 2. Operating points of the different classes 
matching networks transform the input and of current mode PAs [9]. 
output impedance Z0 to the source and load 
 The drain current I exhibits pinch-off, 
impedances Z and Z , respectively. Both D
 S L when the channel is completely closed by the 
input and output matching network are gate-source voltage V and reaches the 
designed for 50 Ωexternal load. GS
 saturation, in which further increase of gate-
 source voltage results in no further increase in 
 drain current. 
 Table 1. Conduction angle of the different classes 
 of current mode PAs [9] 
 Class Conductance Angle 
 A 2 
 AB –2 
 B 
 C 0– 
 Figure 1. Block diagram of PAs. 
 The other very important concept to define 
2.2. Classification of PAs the different classes of current source mode PA 
 is the conduction angle . The conduction 
 There are generally two types of PAs: the angle depicts the proportion of the RF cycle for 
current source mode PAs and the switching which conduction occurs. The conduction 
mode PAs. Different kinds of each mode of angles of different classes are summarized in 
PAs and their functional principles are table 1 while Fig. 3 shows an example of drain 
introduced in detail in [4]. In a current source voltage and current waveforms in an ideal 
 class-B PA. 
mode PA, the power device is regarded as a 
current source, which is controlled by the input 2.3. PA efficiency 
signal. The most important current source mode 
PAs are class A, class B, class AB and class C. Efficiency is a measure of performance of 
They differ from each other in the operating a PA. The performance of a PA will be better if 
points. Fig. 2 illustrates the different classes of its efficiency is higher, irrespective of its 
 definition. The PA is the most 
current source mode PAs in the transfer 
 power-consuming block in a wireless 
characteristic of a FET device. 
 transceiver. 
 T.A. Vu et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 33, No. 1 (2017) 1-7 3 
 Fig. 4 shows the complete circuit of the 
 single-stage cascode PA with all component 
 values are given in table 2. It includes an input 
 matching network, a cascode amplifying stage 
 and an output matching network. Apart from 
 the capability to deliver more output power, the 
 cascode stage alleviates the Miller effect and 
 therefore presents wider bandwidth and better 
 stability than common-source stage. Since PA 
 can be stabilized by maximizing their reverse 
 Figure 3. Drain voltage and current waveforms isolation, the cascode structure is employed in 
 in an ideal class-B PA. this design to further increase input-output 
 reverse isolation and stability. For wideband 
 Its power efficiency has a direct impact on input and output matching, multi-stage 
the battery life of mobile devices. Several matchings using capacitors and inductors are 
definitions of efficiency are commonly used adopted. The capacitors and inductors form 
with PAs. Most widely used measures are the 4th-order high-pass filters at input and output 
drain efficiency and power added efficiency. port. All of the capacitors also act as coupling 
The drain efficiency is defined as capacitors while the DC bias voltages are 
 POUT
  = (1) applied across the inductors L2 and L3 . 
 PDC
 On-chip inductors L1 , L2 , L3 and L4 have 
 where POUT is the RF output power at values of 1.1, 2.8, 2.4 and 0.8 nH, respectively. To 
operating frequency and P the DC power 
 DC operate as a class-B PA, the transistor M1 is 
consumption of the PA output stage. It reveals biased with its gate-source voltage equals to the 
how efficient the PA is when it converts the 
 threshold voltage, VGS = VTH = 420mV . A 
power from DC to AC. The PAE is given by 
 235Ω resistor, R , is added in series to the gate 
 P P G
 PAE = OUT IN (2) 
 of transistor M1 for stabilization. The minimum-
 PDC
 loss cascade stabilizing resistor value is 
 where P is the input power fed to the PA 
 IN determined from the Smith chart by finding the 
and PDC the total DC power consumption of constant resistance that is tangent to the 
the PA. The PAE gets close to  if the gain of appropriate stability circle [5]. 
the PA is sufficient high so that the input power 
is negligible. 
3. Design of 2.4 GHz class-B poweramplifiers 
 The PAs are designed using the TSMC 
0.13µm CMOS mixed-signal/RF process. Its 
back end consists of 8 copper layers and a top 
aluminum redistribution layer (RDL). In order 
to increase the efficiency, the designed PAs are 
biased to operate as class-B PAs. Figure 4. The single-stage class-B cascode PA. 
3.1. Single-Stage class-B cascode PA 
4 T.A. Vu et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 33, No. 1 (2017) 1-7 
 Table 2. Transistor Dimensions, Component characteristic impedance of 71 Ω (the 
 Values and Bias Setting of Single-Stage 71ΩGCPW-TL) is used for the shunt stubs of 
 Class-B Cascode PA the inter-stage matching network. The width of 
 Parameter Value the top-layer signal line is 3.2 µm, and the GND 
 wall placed at a distance 
 1.2 V 
 VDD of 7.3 µm from the signal line has the width of 
 VGS 0.42 V 1.8µm. The 2nd to 4th metal layers are meshed 
 M – M 30µm/130nm and stitched together with vias to form the 
 1 2 GND plane. 
 RG 235Ω 
 C1 2.4 pF 
 C2 0.8 pF 
 C3 0.1 pF 
 C4 1.2 pF 
 L1 1.1 nH 
 L2 2.8 nH 
 L3 2.4 nH 
 L4 0.8 nH 
3.2. Two-Stage class-B cascode PA 
 The single-stage PA employs four on-chip Figure 5. The cross-view of the GCPW 
inductors in the input and output matching transmission line. 
network for bandwidth enhancement. These 
inductors occupy a very large area in the layout Fig. 6 show the complete circuit of the 
and are hard to adapt to finer pitch technology. two-stage cascode PA with all component 
For two-stage PA, each inductor is replaced by values are given in table 3. The cascode 
an equivalent transmission line (TL) for topology reduces the input capacitance of the 
reducing chip area. Although for 2.4 GHz second stage by decreasing the Miller effect due 
frequency band, the lengths of the TLs may be to transistor M1 . In order to double the gain, a 
long. However, the long TLs can be folded for cascade of two cascode stages is used. The 
better area efficiency compared to the RF 
 capacitor C3 blocks the DC offset of the first 
inductor counterparts. amplifying stage to have an independent 
 The cross-view of the grounded coplanar biasing of the second amplifying stage. 
wave-guide transmission line (GCPW-TL) is The DC bias voltages are established 
depicted in Fig. 5. The GCPW-TL with a 
 through the transmission lines TL2 , TL3 , TL4 
characteristic impedance of Z0 of 50 Ω (the 50 
 and . For stabilization, the resistor and 
Ω GCPW-TL) is used for shunt stubs of the TL5 RG1
input/output matching. Its signal line is RG2 is added in series to the gate of transistor 
composed of the RDL layer with a width of 9.5 
 M and M , respectively. 
µm. Ground (GND) walls composed of the 5th 1 3
to 8th metal layers with a width of 2.7µm are The lengths of the TLs and the capacitor 
placed on the both side of the signal line at the values are determined by a nonmetric 
distance of 7µm. The GCPW-TL with optimization process taking into account the 
 models of MOSFETs, MOM capacitors and 
 T.A. Vu et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 33, No. 1 (2017) 1-7 5 
TLs. Many-stage amplifiers for RF 71Ω GCPW-TLs themselves are designed to be 
frequencies tend to occupy a large area since narrow, thereby reducing the footprint. 
inter-stage matching networks consist 
typically of several passive devices that are 
much large than MOSFETs. 4. Simulation results 
 Simulated results of the class-B PAs for 
 TSMC 0.13 µm CMOS technology is achieved 
 using the CADENCE design environment. 
 Circuit design at high frequencies involves 
 more detailed considerations than at lower 
 frequencies when the effect of parasitic 
 capacitances and inductances can impose 
 serious constrains on achievable performance. 
 Figure 6. The two-stage class-B cascode PA. 4.1. Single-Stage class-B cascode PA 
 Table 3. Transistor Dimensions, Component Values Fig. 7 shows the simulated S-parameters of 
 and Bias Setting of Two-Stage Class-B Cascode PA 
 the single-stage cascode PA. S11 remains below 
 17 dB while S22 is less than 20 dB over a -
 Parameter Value 3 dB bandwidth of 2.4–2.48 GHz. Both input 
 VDD 1.2 V and output return loss indicate relatively 
 wideband performance. 
 VGS 0.42 V 
 M1 – M4 30µm/130nm 
 RG1 – RG2 235 Ω 
 C1 0.56 pF 
 C2 0.22 pF 
 C3 0.12 pF 
 C4 0.36 pF 
 C 1.15 pF 
 5 
 TL1 658 µm 
 Figure 7. The simulated S-parameter 
 TL2 1662 µm of the designed single-stage PA. 
 TL 694 µm 
 3 The PA achieves a peak gain of 20.4 dB at 
 1056 µm 
 TL4 2.45 GHz while the reverse isolation is lower 
 TL5 936 µm than -35 dB (not shown in the figure). A high 
 TL 366 µm reverse isolation guarantees high stability for 
 6 the PA. 
 To realize cost-effective chips, area Fig. 8 and Fig. 9 show the drain efficiency 
reduction is important. In order to reduce the and PAE versus input power, respectively. The 
area of the amplifier, the 71 Ω GCPW-TLs used designed PA obtains a peak drain efficiency of 
in the inter-stage matching network are 36.6% at -10 dBm input power. It corresponds 
arranged regularly at narrow spacings, and the to a peak PAE of 35.4%. The linearity of the 
6 T.A. Vu et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 33, No. 1 (2017) 1-7 
single-stage PA in term of input referred 1 dB 
compression point (IP1dB) is -8.8 dBm. The 
single-stage PA consumes only 4.5 mW from a 
1.2 V supply voltage. 
 Figure 10. The simulated S-parameter of the 
 designed two-stage PA. 
 Fig. 11 and Fig. 12 show the drain 
 Figure 8. The simulated drain efficiency of the 
 designed single-stage PA. efficiency and PAE versus input power, 
 respectively. The peak drain efficiency drops to 
 25.4% corresponding to the peak PAE of 24.1% 
 at –21 dBm input power. The IP1dB is -24.5 
 dBm. The two-stage PA consumes only 9 mW 
 from a 1.2 V supply voltage. Table 4 
 summarizes the performance of the proposed 
 PAs and compares them to other published 
 designs operating in a similar frequency range. 
 Both proposed PAs are unconditionally stable 
 at all frequencies. 
 Figure 9. The simulated PAE of the designed 
 single-stage PA. 
4.2. Two-Stage Class-B Cascode PA 
 Fig. 10 shows the simulated S-parameters 
of the two-stage cascode PA. S11 is less than 
 18 dB while S22 is less than 15 dB over a -
3 dB bandwidth from 2.4 GHz to 2.48 GHz. 
The PA achieves a high gain of 37.7 dB at 
 2.45 GHz while the reverse isolation is lower Figure 11. The simulated drain efficiency of the 
than -35 dB. designed two-stage PA. 
 J 
 Figure 12. The simulated PAE of the designed two-stage PA. 
 T.A. Vu et al. / VNU Journal of Science: Comp. Science & Com. Eng., Vol. 33, No. 1 (2017) 1-7 7 
 Table 4. Comparison with previous published PAs operating at 2.4 GHz band 
 Parameter [3] [1] [10] [7] [8] This work 1 This work 2 
 CMOS technology 90 nm 65 nm 0.18 µm 0.18 µm 0.18 µm 0.13µm 0.13 µm 
 Supply voltage (V) 3.3 3.3 5.6 1.8 2.4 1.2 1.2 
 Gain (dB) 28 32 21.4 10.4 18 20.4 37.7 
 Peak PAE (%) 33 25 26.1 16.2 24.6 35.4 24.1 
 IP1dB (dBm) 0 7 5.6 13 7.5 -8.8 -24.5 
p 
5 Conclusions [3] D. Chowdhury, C. D. Hull, O. B. Degani, and Y. 
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 [7] H. Magnusson and H. Olsson, “A compact 
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