2D parity product code for TSV online fault correction and detection

ional Founda-
inserting faults in each gate of the design. Instead of
usesmall the number brute-force of gates simulation in both to encoder find out and the decoder, detection we tionThis forAcknowledgment Scienceresearch and is fundedTechnology byVietnam Development National (NAFOS- Founda-
usinguse the a brute-force Monte-Carlo simulation simulation to find as in out [44], the detection due to the tion for Science and Technology Development (NAFOS-
small number of gates in both encoder and decoder, we This research is funded by Vietnam National Founda-
use the brute-force simulation to find out the detection tion for Science and Technology Development (NAFOS-
coverage. In order to test the correctness of the encoder TED) under grant number 102.01-2018.312.
20 REV Journal on Electronics and Communications, Vol. 10, No. 1–2, January–June, 2020
References [17] B. Fu and P. Ampadu, “On hamming product codes with
 type-ii hybrid ARQ for on-chip interconnects,” IEEE
 [1] J. Cho, E. Song, K. Yoon, J. S. Pak, J. Kim, W. Lee, Transactions on Circuits and Systems I: Regular Papers,
 T. Song, K. Kim, J. Lee, H. Lee et al., “Modeling and vol. 56, no. 9, pp. 2042–2054, 2009.
 analysis of through-silicon via (TSV) noise coupling [18] A. B. Ahmed and A. B. Abdallah, “Architecture and de-
 and suppression using a guard ring,” IEEE Transactions sign of high-throughput, low-latency, and fault-tolerant
 on Components, Packaging and Manufacturing Technology, routing algorithm for 3D-network-on-chip (3D-NoC),”
 vol. 1, no. 2, pp. 220–233, 2011. The Journal of Supercomputing, vol. 66, no. 3, pp. 1507–
 [2] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, 1532, 2013.
 J. Lee, H. Lee, K. Park et al., “High-frequency scalable [19] ——, “Adaptive fault-tolerant architecture and routing
 electrical model and analysis of a through silicon via algorithm for reliable many-core 3D-NoC systems,” Jour-
 (TSV),” IEEE Transactions on Components, Packaging and nal of Parallel and Distributed Computing, vol. 93, pp. 30–
 Manufacturing Technology, vol. 1, no. 2, pp. 181–195, 2011. 43, 2016.
 [3] X. Dong and Y. Xie, “System-level cost analysis and de- [20] K. N. Dang, A. B. Ahmed, Y. Okuyama, and A. B. Abdal-
 sign exploration for three-dimensional integrated circuits lah, “Scalable design methodology and online algorithm
 (3D ICs),” in Proceedings of the Asia and South Pacific for TSV-cluster defects recovery in highly reliable 3D-
 Design Automation Conference, 2009, pp. 234–241. NoC systems,” IEEE Transactions on Emerging Topics in
 [4] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, Computing, 2017.
 A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying [21] Y. Lou, Z. Yan, F. Zhang, and P. D. Franzon, “Comparing
 3D ICs: The pros and cons of going vertical,” IEEE Design through-silicon-via (TSV) void/pinhole defect self-test
 & Test of Computers, vol. 22, no. 6, pp. 498–510, 2005. methods,” Journal of Electronic Testing, vol. 28, no. 1, pp.
 [5] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, 27–38, 2012.
 M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, [22] M. Tsai, A. Klooz, A. Leonard, J. Appel, and P. Franzon,
 R. Sirdeshmukh, E. J. Sprogis et al., “Three-dimensional “Through silicon via (TSV) defect/pinhole self test cir-
 silicon integration,” IBM Journal of Research and Develop- cuit for 3D-IC,” in Proceedings of the IEEE International
 ment, vol. 52, no. 6, pp. 553–569, 2008. Conference on 3D System Integration, 2009, pp. 1–8.
 [6] U. Kang, H.-J. Chung, S. Heo, D.-H. Park, H. Lee, J. H. [23] B. Noia and K. Chakrabarty, “Pre-bond probing of TSVs
 Kim, S.-H. Ahn, S.-H. Cha, J. Ahn, D. Kwon et al., “8 Gb in 3D stacked ICs,” in Proceedings of the IEEE International
 3-D DDR3 DRAM using through-silicon-via technology,” Test Conference, 2011, pp. 1–10.
 IEEE Journal of Solid-State Circuits, vol. 45, no. 1, pp. 111– [24] P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-chip TSV
 119, 2010. testing for 3D IC before bonding using sense amplifica-
 [7] G. Van der Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, tion,” in Proceedings of the Asian Test Symposium. IEEE,
 C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti 2009, pp. 450–455.
 et al., “Design issues and considerations for low-cost 3- [25] M. Y. Hsiao, D. C. Bossen, and R. T. Chien, “Orthogonal
 D TSV IC technology,” IEEE Journal of Solid-State Circuits, latin square codes,” IBM Journal of Research and Develop-
 vol. 46, no. 1, pp. 293–307, 2011. ment, vol. 14, no. 4, pp. 390–394, 1970.
 [8] F. Ye and K. Chakrabarty, “TSV open defects in 3D [26] K. N. Dang, M. C. Meyer, A. B. Ahmed, A. B. Abdallah,
 integrated circuits: Characterization, test, and optimal and X.-T. Tran, “2D-PPC: A single-correction multiple-
 spare allocation,” in Proceedings of the Design Automation detection method for through-silicon-via faults,” in Pro-
 Conference. ACM, 2012, pp. 1024–1030. ceedings of the IEEE Asia Pacific Conference on Circuits and
 [9] K. N. Dang and A. B. Abdallah, “Architecture and Systems, 2019, pp. 109–112.
 Design Methodology for Highly-Reliable TSV-NoC Sys- [27] Y. Zhao, S. Khursheed, and B. M. Al-Hashimi, “Online
 tems,” in Horizons in Computer Science Research. Nova Fault Tolerance Technique for TSV-Based 3-D-IC,” IEEE
 Science Publishers, 2018, vol. 16, pp. 199–246. Transactions on Very Large Scale Integration (VLSI) Systems,
[10] L. Jiang, Q. Xu, and B. Eklow, “On effective through- vol. 23, no. 8, pp. 1567–1571, 2014.
 silicon via repair for 3-D-stacked ICs,” IEEE Transactions [28] A. Dutta and N. A. Touba, “Multiple bit upset tolerant
 on Computer-Aided Design of Integrated Circuits and Sys- memory using a selective cycle avoidance based SEC-
 tems, vol. 32, no. 4, pp. 559–571, 2013. DED-DAEC code,” in Proceedings of the 25th IEEE VLSI
[11] R. Kumar and S. P. Khatri, “Crosstalk avoidance codes Test Symposium (VTS’07). IEEE, 2007, pp. 349–354.
 for 3D VLSI,” in Proceedings of the Design, Automation & [29] L.-J. Saiz-Adalid, P. Reviriego, P. Gil, S. Pontarelli, and
 Test in Europe Conference & Exhibition. EDA Consortium, J. A. Maestro, “MCU tolerance in SRAMs through low-
 2013, pp. 1673–1678. redundancy triple adjacent error correction,” IEEE Trans-
[12] A. Eghbal, P. M. Yaghini, N. Bagherzadeh, and actions on Very Large Scale Integration (VLSI) Systems,
 M. Khayambashi, “Analytical fault tolerance assessment vol. 23, no. 10, pp. 2332–2336, 2015.
 and metrics for TSV-based 3D network-on-chip,” IEEE [30] K. N. Dang, A. B. Ahmed, and X. T. Tran, “An
 Transactions on Computers, vol. 64, no. 12, pp. 3591–3604, on-communication multiple-TSV defects detection and
 2015. localization for real-time 3D-ICs,” in Proceedings of
[13] Y. J. Park, M. Zeng, B.-s. Lee, J.-A. Lee, S. G. Kang, and the IEEE 13th International Symposium on Embedded
 C. H. Kim, “Thermal analysis for 3D multi-core proces- Multicore/Many-core Systems-on-Chip (MCSoC), 2019, pp.
 sors with dynamic frequency scaling,” in Proceedings of 223–228.
 the IEEE/ACIS 9th International Conference on Computer [31] K. N. Dang, A. B. Ahmed, A. B. Abdallah, and X.-T.
 and Information Science (ICIS), 2010, pp. 69–74. Tran, “TSV-OCT: A Scalable Online Multiple-TSV De-
[14] M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopad- fects Localization for Real-Time 3-D-IC systems,” IEEE
 hyay, “Design method and test structure to characterize Transactions on Very Large Scale Integration (VLSI) Systems,
 and repair TSV defect induced signal degradation in 2019.
 3D system,” in Proceedings of the IEEE/ACM International [32] K. N. Dang, A. B. Ahmed, B. A. Abderrazak, and X.-T.
 Conference on Computer-Aided Design, 2010, pp. 694–697. Tran, “TSV-IaS: Analytic Analysis and Low-Cost Non-
[15] R. W. Hamming, “Error detecting and error correcting Preemptive on-Line Detection and Correction Method
 codes,” Bell System Technical Journal, vol. 29, no. 2, pp. for TSV Defects,” in Proceedings of the IEEE Computer
 147–160, 1950. Society Annual Symposium on VLSI, 2019, pp. 501–506.
[16] M.-Y. Hsiao, “A class of optimal minimum odd-weight- [33] S. B. Wicker and V. K. Bhargava, Reed-Solomon codes and
 column SEC-DED codes,” IBM Journal of Research and their applications. John Wiley & Sons, 1999.
 Development, vol. 14, no. 4, pp. 395–401, 1970. [34] I. S. Reed and X. Chen, Error-control coding for data
K. N. Dang et al.: 2D Parity Product Code for TSV Online Fault Correction and Detection 21
 networks. Springer Science & Business Media, 2012, vol. Akram Ben Ahmed received his M.S.E. and
 508. Ph.D. degrees in Computer Science and En-
[35] R. M. Pyndiah, “Near-optimum decoding of product gineering from the University of Aizu, Japan,
 codes: Block turbo codes,” IEEE Transactions on Commu- in 2012 and 2015, respectively. He is currently
 nications, vol. 46, no. 8, pp. 1003–1010, 1998. with National Institute of Advanced Industrial
 Science and Technology (AIST), Japan. He was
[36] F. Chiaraluce and R. Garello, “Extended Hamming prod- a postdoctoral researcher in the Department of
 uct codes analytical performance evaluation for low error Information and Computer Science, Keio Uni-
 rate applications,” IEEE Transactions on Wireless Commu- versity, Japan from 2014 to 2019. His current
 nications, vol. 3, no. 6, pp. 2353–2361, 2004. research interests include on-chip intercon-
[37] J. F. Ziegler and W. A. Lanford, “Effect of cosmic rays nection networks, reliable and fault-tolerant
 on computer memories,” Science, vol. 206, no. 4420, pp. systems, and ultra-low-power embedded real-time systems.
 776–788, 1979.
[38] T. C. May and M. H. Woods, “A new physical mecha-
 nism for soft errors in dynamic memories,” in Proceedings
 of the 16th International Reliability Physics Symposium, Abderazek Ben Abdallah Abderazek Ben
 1978, pp. 33–40. Abdallah is a full Professor of Computer
[39] J. Sosnowski, “Transient fault tolerance in digital sys- Science and Engineering and the Head of
 tems,” IEEE Micro, vol. 14, no. 1, pp. 24–35, 1994. the Division of Computer Engineering, the
[40] K. Chakrabarty, S. Deutsch, H. Thapliyal, and F. Ye, University of Aizu. He has been a faculty
 “TSV defects and TSV-induced circuit failures: The third member at the University of Aizu since 2007.
 dimension in test and design-for-test,” in Proceedings of Before joining the University of Aizu, he was
 the IEEE International Reliability Physics Symposium, 2012, a research associate at the Graduate School
 pp. 5F–1. of Information Systems, the Univ. of Electro-
 Communications at Tokyo from 2002 to 2007.
[41] K. A. Bowman, J. W. Tschanz, N. S. Kim, J. C. Lee, C. B. He received the h.D. degree in computer engi-
 Wilkerson, S.-L. L. Lu, T. Karnik, and V. K. De, “Energy- neering from the Univ. of Electro-Communications at Tokyo in 2002.
 efficient and metastability-immune resilient circuits for His research falls primarily in the area of computer system and
 dynamic variation tolerance,” IEEE Journal of Solid-State architecture, with an emphasis on adaptive/self-organizing systems,
 Circuits, vol. 44, no. 1, pp. 49–63, 2009. networks-on-chip/SoCs, processor micro-architecture and power &
[42] S. E. Lee, Y. S. Yang, G. S. Choi, W. Wu, and R. Iyer, reliability-aware architectures. He is also interested in neuro-inspired
 “Low-power, resilient interconnection with orthogonal systems and VLSI design for 3D-ICs. He has authored three books,
 latin squares,” IEEE Design & Test of Computers, vol. 28, published more than 150 journal articles and conference papers in
 no. 2, pp. 30–39, 2011. these areas and given invited talks as well as courses at several
 universities. He has been a PI or CoPI of several projects for devel-
[43] A. Stillmaker and B. Baas, “Scaling equations for the oping next generation high-performance reliable computing systems
 accurate prediction of CMOS device performance from for applications in general purpose and pervasive computing. He is
 180 nm to 7 nm,” Integration, vol. 58, pp. 74–81, 2017. a senior member of IEEE and ACM and a member of IEICE.
[44] K. N. Dang, A. B. Ahmed, X.-T. Tran, Y. Okuyama,
 and A. B. Abdallah, “A comprehensive reliability assess-
 ment of fault-resilient network-on-chip using analytical
 model,” IEEE Transactions on Very Large Scale Integration
 (VLSI) Systems, vol. 25, no. 11, pp. 3099–3112, Nov 2017. Xuan-Tu Tran received a Ph.D. degree in
 2008 from Grenoble INP (at the CEA-LETI),
 France, in Micro Nano Electronics. He is cur-
 rently an associate professor at VNU Uni-
 versity of Engineering and Technology, Viet-
 Khanh N. Dang is currently an assistant nam National University, Hanoi (VNU). He
 professor at VNU Key Laboratory for Smart was an invited professor at the University
 Integrated Systems, Vietnam National Univer- Paris-Sud 11, France (2009, 2010, and 2015),
 sity Hanoi (VNU), Hanoi Vietnam. He re- University of Electro-Communication, Tokyo
 ceived his B.Sc., M.Sc., and Ph.D. degree from (2019), Grenoble INP (2011, 2020), and adjunct
 VNU University of Engineering and Tech- professor at University of Technology Sydney
 nology, University of Paris-Sud XI, and The (2017-2020). He is currently Director for the VNU Key Laboratory
 University of Aizu, Japan in 2011, 2014, and for Smart Integrated Systems (SISLAB). His research interests include
 2017, respectively. Dr. Khanh N. Dang was design and test of systems-on-chips, networks-on-chips, design-for-
 visiting researcher at University of Aizu in testability, asynchronous/synchronous VLSI design, low power tech-
 2019. His research interests include System- niques, and hardware architectures for multimedia applications. He
on-Chips/Network-on-Chips, 3D-ICs, and fault-tolerant systems. has published more than 80 journal articles and conference papers
 in these areas and given invited talks as well as courses at several
 universities.
 He is a Senior Member of the IEEE, IEEE Circuits and Systems
 (CAS), IEEE Solid-State Circuits and Systems (SSCS), member of
 Michael Meyer is currently an Assistant Pro- IEICE, and the Executive Board of the Radio Electronics Association
 fessor at Waseda University. He was previ- of Vietnam (REV). He serves as Chairman of IEICE Vietnam Section,
 ously a post-doctoral researcher at the Uni- Chairman of IEEE SSCS Vietnam Chapter.
 versity of Aizu in Fukushima, Japan, as a
 member of the Data Networking Laboratory.
 He graduated from Rose-Hulman Institute of
 Technology, in Indiana, USA, with a B.S. in
 Computer Engineering in 2012, and then with
 a M.A. in Engineering Management in 2013.
 In 2017 he received a Ph.D. in Comp. Sci.
 and Eng. from the University of Aizu. He has
worked for Texas Instruments before starting his Ph.D., and before
that he had worked for Syntheon developing biomedical devices.
His research interests cover on and off chip networks, reliability and
photonics.