Applications of tcad simulation software to the study of floating - gate device

n results at programming and
erasing states are presented in section 4. The last section gives the conclusion.
2. Floating Gate Device
Floating-gate devices are at the core of almost every modern non-volatile memories
[6]. Non-volatile memory describes a system where the contents of the memory are
retained after the power is switched off. In silicon integrated circuit technology, non-
volatile memories are realized through the use of an electrically isolated “floating gate”,
which is electrically isolated from the gate and substrate by an insulator. A cross-section
schematic shown in Figure 1 illustrates a floating-gate device [9]. The state of this
device depends on the charge on a floating gate. These states are reading, programming
(writing) and erasing. More importantly, the insulator around the floating gate must be
thick enough to prevent the floating gate from discharging when the power is removed,
and it also must be thin enough to allow the transfer of charge on and off the floating
gate under appropriate bias configuration.
Fig. 1. Cross section schematic of a floating-gate device
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Table 1. Floating-gate device operations
Program (Write) [Channel Hot Electron Injection] Erase [Fowler Nordheim Tunnel] Read
The operations of the floating-gate device are presented in the following table [10].
Programming refers to putting charge on the floating gate, erasing refers to removing
the charge from the gate, and reading involves sensing the electrical signal of the cell
to determine if the device is programmed or erased.
2.1. Read Operation
The read operation is performed by applying a gate voltage that is between the values
of the erased and programmed threshold voltages and sensing the current flow through
the device [6].
Fig. 2. Floating-gate reading operation
In Figure 2, Vth”1” is the threshold voltage of the floating-gate device at the erasing
state and Vth”0” is the threshold voltage of the floating-gate at the programming state.
The threshold voltage shift ∆Vth is determined according to the formula below:
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∆Vth =
−(Qth”0”−Qth”1”)
Cpp
(1)
where Qth”0” is the charge on the floating gate when the floating-gate device at
programming state, Qth”1” is the charge on the floating gate when the floating-gate
device at erasing state, Cpp is the capacitance between the control gate and floating
gate.
2.2. Program Operation
The program operation is performed when electrons move from the substrate to
the floating gate. These electrons are called Channel Hot Electrons. The Channel Hot
Electron current includes the CHE and the CHISEL currents.
Qualitatively, to contribute to CHE and CHISEL currents, such electrons must gain
from the lateral field sufficient kinetic energy to be able to overcome the Si/SiO2
barrier, and their momentum has to be directed toward the gate for the hot electrons to
be collected at the gate [6]. The program operation is illustrated in Figure 3.
Fig. 3. Floating-gate programming operation
2.3. Erase Operation
The erase operation is performed when electrons move from the floating gate cross
the tunnel oxide to the substrate under the appropriate bias configuration. The electron
current is called Fowler-Nordheim Tunnel current [6]. The figure bellow demonstrates
the configuration for erase operation.
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Fig. 4. Floating-gate erasing operation
3. Floating Gate Fabrication Steps
The detailed process flow to fabricate a floating-gate device with P-type substrate for
180nm CMOS process is presented in Figure 5.
Fig. 5. Floating-gate device design flow chart
This flow proposes using an addition Epitaxial grow layer which was not used in
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traditional CMOS processes. The growth of an epitaxial layer over the P-type substrate
offers some advantages including improving the performance of this device as well as
floating-gate integrated circuits, minimizing latch-up effects that a CMOS circuit may
undergo when powered up, and helping control the doping concentration of this device
accurately [11].
The main difference in terms of structure between the floating-gate device and CMOS
device is that the floating-gate device has an additional floating gate which is created
by two steps: Deposit Polysilicon (Floating gate), Dope Polysilicon (Floating gate) in
the flow.
These figures below illustrate the main process simulations using TCAD based on
the design flow chart presented above (Figure 6a-6h).
ATHENA is used to generate a mesh to simulate 2D CMOS process including the
structure, doping profile, and contact area. ATHENA provides general capabilities for
numerical, physically-based, 2D simulation of a semiconductor process. It can perform
structure initialization and manipulation, basic deposition, etch facilities, and user-
defined model for implantation and diffusion [12].
The fabrication process starts from creating P-substrate (initial surface thickness =
1µm) with Boron at a concentration of 1.0e14 cm−3 (Figure 6a). Next, a mesh is
defined, and the density of the mesh is a trade-off between accuracy and simulation
time. After the mesh and wafer definition, a 0.45µm thick Epitaxy layer with Arsenic
at a concentration of 1.0e16 cm−3 is grown on the top to make device surface thickness
increase to 1.45µm (Figure 6b). Then, a P well is implanted using Boron with a dose
of 8e12 cm−3. After that, the P well is also diffused with Nitro gas at 1200oC for about
310 minutes (Figure 6c). Next, Locos and tunnel oxide layer are created (Figure 6d).
Creating Locos is an important step in the fabrication of semiconductor devices for the
purpose of isolating the operation of two devices on the same wafer, and Oxide is usually
used for this isolation. The doping channel is created using Boron at 100KeV and a
concentration of 2.5e12 cm−3 (Figure 6e). Figure 6f shows the device structure after
Polysilicon (Floating gate) is deposited and doped. Figure 6g shows the device structure
after Polysilicon (Control gate) is deposited and doped. The Floating gate, Control gate,
Tunnel Oxide layer and Oxide-Nitride-Oxide layer which is between Floating gate and
Control gate are etched. An oxide layer with a thickness of 0.1µm is deposited and
etched on the top to protect the device by the next steps. The next step is to create
Source and Drain gates with Arsenic at 50 KeV and a concentration of 7e12 cm−3
(Figure 6h). After growing the protection layer, the final step is to deposit and etch
Aluminum contacts for Source and Drain gates. The complete 2D floating-gate device
is presented in Figure 7.
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(a) Definition wafer (b) Grow Epitaxial layer
(c) P well drive (d) After creating Locos and grow Gate oxide
(e) Dope channel (f) Create Floating gate and dope polysilicon
(g) Create Control gate and dope polysilicon (h) After implant and diffuse S/D dopants
Fig. 6. The main process simulations with TCAD including in a) Definition wafer b) Grow Epitaxial
layer c) P well drive d) After creating Locos and grow Gate oxide e) Dope channel f) Create Floating
gate and dope polysilicon g) Create Control gate and dope polysilicon h) After implant and
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Fig. 7. The 2D structure of the floating-gate device
The 3D structure of the floating-gate device is created from the 2D structure and the
value of width by using DEVEDIT3D tool. The 3D structure of the floating-gate device
is shown in Figure 8.
Fig. 8. The 2D structure of the floating-gate device
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4. Simulation Results
ATLAS is a physically-based two and three-dimensional device simulator that pre-
dicts the electrical behavior of semiconductor devices at specified bias conditions. The
physical structure created using ATHENA tool is used as the input for ATLAS tool.
The combination of ATHENA and ATLAS makes it possible to simulate and extract the
device characteristics [12]. These figures below show the characteristics of the floating-
gate device at the programming state and the erasing state.
Fig. 9. Threshold voltage before programming
Initially, no charge is stored on the floating-gate (Q = 0) and before programming,
the threshold voltage of the floating-gate device is 0.6V (Figure 9).
Fig. 10. Floating gate charge in programming
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Fig. 11. Threshold voltage after programming
The transient simulation for the charge on the floating gate is shown in Figure 10. In
order to perform the simulation, the voltage of the Control gate is 12V, the Drain gate
is 5.85V, and the Source gate is 0V.
The amount of negative charge on the floating gate increases from 0 (C) to -3.5e-15
(C) as the electron moves from the substrate to the floating gate. The electron flow
consists of two currents CHE and CHISEL shown in Section 2. At the same time, after
programming, the threshold voltage of the floating-gate device increases from 0.6V to
approximately 6V (Figure 10-11).
Fig. 12. Floating gate charge in erasing
To perform the transient simulation for the charge on the floating gate during the
erasing state, the voltage of the Control gate is -15V, the Drain gate is 0V, and the
Source gate is 15V.
After erasing, electrons on the floating gate move from the floating gate to the
substrate, causing the amount of charge in the floating gate to change from -3.5e-15
(C) to 0 (C). Fowler-Nordheim is the flow of electrons moving from the floating gate
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to the substrate and presented in Section 2.
5. Conclusion
In this paper, a detailed design flow chart is suggested to fabricate the floating-gate
device in TCAD environment. This paper is successful in studying the structure and
operation of the floating-gate device. All of the process steps including ATHENA, AT-
LAS, and DEVEDIT3D commands are performed to simulate the 2D and 3D structure
and the device characteristics. The results of the transient programming and erasing
simulations worked as expected.
References
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IEEE Trans. Circuits Syst.II Exp. Papers, vol. 61, no. 10, pp. 763-767, Oct. 2014.
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Compon. Lett., vol. 26, no. 3, pp. 201-203, Mar. 2016.
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misalignment sensor in silicon technology", IEEE Sensors J., vol. 17, no. 5, pp. 1211-1212, Mar. 2017.
[4] S. Chakraborty et al., "A broadside-coupled meander-line resonator in 0.13-µm SiGe technology for millimetre-
wave application", IEEE Electron Devices Lett., vol. 37, no. 3, pp. 329-331, Mar. 2016.
[5] R. Bez, E. Camerlenghi, A. Modelli and A. Visconti, “Introduction to Flash Memory”, IEEE vol. 91, no. 4,
April 2003.
[6] P. Pavan, L. Larcher and A. Marmiroli, “Floating Gate Devices: Operation and Compact Modeling”, pp.18-82,
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[7] Y. Saad, C. Tavernier, M. Ciappa and W.Fichtner, “TCAD tools for efficient 3D simulations of geometry effects
in floating-gate structures”, IEEE Computational Systems Bioinformatics Conference, 2004.
[8] S. Bala and B. Mahendia, “Simulation of Floating Gate MOSFET Using Silvaco TCAD Tools”, IRACST-
Engineering Science and Technology: An International Journal, vol. 5, no. 4, Aug. 2015.
[9] S. Keeney, R. Bez, D. Cantarelli, F. Piccinini, A. Mathewson, L. Ravazzi and C. Lombardi, “Complete Transient
Simulation of Flash EEPROM Devices”, IEEE Transactions on Electron Devices, vol. 39, no.12, Dec. 1992.
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Manuscript received 22-03-2019; Accepted 18-12-2019.

Dang Cong Thinh was born in Binh Dinh province, Vietnam. He received the Bachelor
of Engineering, and Master of Science degree in Electronics-Telecommunication Engineering
from Ho Chi Minh City University of Technology in 2017 and 2019, respectively. Currently, he
works as Teaching Assistant at Department of Electronics Engineering, Faculty of Electrical-
Electronics Engineering, Ho Chi Minh City University of Technology. His research focuses
on SOC architecture, IC fabrication, Synthesis methodology, Physical Design.
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Section on Information and Communication Technology (ICT) - No. 14 (10-2019)
Mai Tri Hao is a senior student in Electronics-Telecommunication Engineering from Ho Chi
Minh City University of Technology. During 2016 up to now, he has worked as a member of
IC design laboratory in Department of Electronics Engineering. His research focuses on IC
fabrication, Physical Design.
Hoang Trang was born in Nha Trang city, Vietnam. He received the Bachelor of Engineering,
and Master of Science degree in Electronics-Telecommunication Engineering from Ho Chi
Minh City University of Technology in 2002 and 2004, respectively. He received the Ph.D.
degree in Microelectronics-MEMS from CEA-LETI and University Joseph Fourier, France,
in 2009. From 2009–2010, he did the postdoctorate research in Orange Lab-France Telecom.
Since 2010, he is lecturer at Faculty of Electricals–Electronics Engineering, Ho Chi Minh
City University of Technology. His field of research interest is in the domain of FPGA
implementation, Speech Recognizer, IC architecture, MEMS, fabrication.
ỨNG DỤNG CỦA PHẦN MỀMMÔ PHỎNG TCAD
TRONG NGHIÊN CỨU LINH KIỆN CỰC CỔNG NỔI
Tóm tắt
Trong những năm gần đây, linh kiện cực cổng nổi đã trở thành một thành phần thiết lập
trong hầu hết tất cả các hệ thống điện tử, đặc biệt trong các bộ nhớ Non-volatile. Bài báo
này đưa ra một nghiên cứu về cấu trúc và hoạt động (đọc, lập trình/ghi và xóa) của linh kiện
cực cổng nổi. Một quy trình chế tạo cấu trúc 2D và 3D hoàn chỉnh cho linh kiện cực cổng
nổi sử dụng công cụ ATHENA, ATLAS và DEVEDIT3D được đề xuất trong bài báo này.
Các mô phỏng bao gồm đặc tính I-V, Channel Hot Electron Injection, và Fowler-Nordheim
Tunnel được thực hiện trong môi trường TCAD.
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